1. Field of the Invention
The present invention relates generally to computer memory systems, and more particularly, to methods and systems for moving data between two memory locations.
2. Description of the Related Art
Computer memory systems are very common and are used in many different configurations. A typical block of memory includes a block of memory cells and input and output circuitry that allows the block of memory cells to communicate with a device or system that is external to the block of memory.
FIG. 1A shows a typical microprocessor 100. The microprocessor 100 includes a first block of memory 110 includes a block of memory cells 102 and a block of input and output (I/O) circuitry 104. Each one of the memory cells 102 includes a storage circuit 112 (e.g., cross-coupled inverters), one or more keeper circuits 114, and pre-charge circuits 116. The storage circuit 112 stores a selected voltage level that corresponds to a logic value of 1 or 0. The keeper circuits 114 assist the storage circuit 112 in maintaining the selected voltage level. The pre-charge circuits 116 pre-charge the bit lines that are used to read and/or write the voltage level stored in the storage circuit 112.
Typically, the storage circuit 112 stores one of two voltage levels. Typically a low voltage level corresponds to a logical “0” value and a high voltage level corresponds to a logical “1” value. The actual voltage of the high voltage level and the low voltage level is a function of the design (i.e., type) of the storage circuit 112. By way of example, in a first-type of storage circuit 112 a voltage lower than 0.3 volts could be considered a low voltage level and therefore a logical 0. Similarly, a voltage higher than 0.6 volts could be considered a high voltage level and therefore a logical 1 in the first-type storage circuit 112. Conversely, in a second-type storage circuit 112 a voltage greater than 0.3 volts could be considered a high voltage level and therefore a logical 1. Similarly, the second-type storage circuit 112 would require a low voltage level of less than about 0.1 or 0.2 to indicate low voltage level that would correspond to a logical 0.
The block of I/O circuitry 104 includes a sense amplifier 122 on the read line and a write amplifier 124 on a write line. The sense amplifier 122 detects the voltage level of the logic stored in the storage circuit 112 and amplifies the detected the voltage level. The sense amplifier 122 can then communicate the voltage level stored in the storage circuit 112 to an external device such as a bus 130. By way of example, the sense amplifier 122 can detect a voltage level that corresponds to a logical 1 (e.g., greater than about 0.6 volts) stored in the second-type storage circuit 112. The circuits external to the first block of memory 110 may be designed to recognize voltage level of about 1 volt to represent a logical 1. Therefore, the sense amplifier 122 amplifies the detected 0.6 volts to about 1 volt so as to accurately transmit the data value stored in the second-type storage circuit 112.
Similarly, the write amplifier 124 detects and amplifies a voltage level on an external device (e.g., bus 130) and communicates the amplified voltage level to the storage circuit 112. By way of example, a logical voltage of about 0.3 volts is detected on the bus 130 by the write amplifier 124. The write amplifier 124 must accurately discriminate whether the detected 0.3 volts represents a logical one or a logical zero. The write amplifier 124 then modifies (e.g., amplify or reduce) the detected 0.3 volt logic value to either a logical 1 voltage level or a logical 0 voltage level that can be accurately stored in the storage circuit 112.
The microprocessor 100 can also include a second block of memory 140 and a processor core 150. The second block of memory 140 and the processor core 150 can also be coupled to the bus 130. The second block of memory 140 includes a second storage circuit 142. As the processor core 150 performs logical operations, it is often necessary to swap the data from the first block of memory 110 to the second block of memory 140 via the bus 130.
FIG. 1B is a flowchart diagram of the method operations 160 of performing the data swap operation form the first memory 110 to the second memory 140. In an operation 162, the sense amplifier 122 must detect the data voltage level stored in the storage circuit 112. In an operation 164, the sense amplifier 122 amplifies the detected data voltage level. In an operation 166, the amplified data voltage level is communicated across the bus 130 to the second block of memory 140. In an operation 168, the write amplifier 124 detects the communicated voltage level on the bus 130. In an operation 170, the write amplifier 124 amplifies the detected voltage level. In an operation 172, the amplified voltage level is stored in the second storage circuit 142.
The method operations 160 of performing the data swap is a very complex and time consuming process as the data voltage level must be amplified and detected multiple times and communicated a relatively long distance across the bus 130. This time consuming process slows down the effective speed of the processor core 150. Further, the sense amplifiers 122 and write amplifiers 124 are relatively large devices (e.g., typically more than 50 or even 100 times the device sizes of the devices that form the storage circuits 112 and 142) and thereby consume excess space on the semiconductor substrate upon which the microprocessor 100 is formed.
Typically, the sense amplifier 122, the write amplifier 124, the keeper circuits 114 and the pre-charge circuits 116 have substantially larger physical size than the devices (e.g., transistors, inverters, PMOS, NMOS, etc.) that form the storage circuit 112. By way of example, the devices that form the storage circuit 112 can have a width of about 0.5 or 0.3 micron or even smaller. In comparison the keeper circuits 114 and the pre-charge circuits 116 can have a width of about 40–50 micron and the sense amplifier 122, the write amplifier 124 can have a width of about 100 micron or greater. These large device sizes 122 and 124 exacerbate the problem by causing the bus 130 (or other interconnecting circuits and conductive lines) to be larger and longer and the memory blocks 110 and 140 further apart and further from the processor core 150. These large device sizes 122 and 124 further limit the number of memory blocks that can be included on the microprocessor 100.
In view of the foregoing, there is a need for a more efficient system and method for moving data between multiple memory blocks.